The present invention relates to an optical interconnection technique for semiconductor devices having a semiconductor chip and a wiring substrate, or more in particular to a clock signal supply system for a ultra-high-speed processor of the computer.
With the increase in the scale of semiconductor devices, a higher-density assembly and a greater number of input and output terminals of the semiconductor chip are sought. In order to meet this requirement, a flip-chip connection system is conventionally used as disclosed in JP-A-61-177738 based on U.S. patent application Ser. No. 695,597 filed Jan. 28, 1985. In this connection system, the semiconductor chip is connected by bump electrodes on a wiring substrate. Electrodes can be installed over the entire surface of the semiconductor chip, thereby making multi-channel connections possible.
An increased internal operating speed of the semiconductor devices has come to pose the problem of propagation delay time and crosstalks in the electric interconnections of the substrate. For solving this problem, conventional optical interconnection techniques as described in J. W. Goodman et al. "Optical Interconnections for VLSI Systems", C. T. Sullivan et al. "Integrated optics approach for high-density optical interconnections in high-speed multichip IC packages", and Y. Yamada et al. "Optical interconnections using silica-based waveguide on Si substrate" are known. In these optical interconnection techniques, optical waveguides are used for interconnecting semiconductor chips. For lack of an increased time constant due to a capacitor and a resistor or crosstalks due to induction unlike in electrical connections, optical waveguides are said to permit high-speed, broad-band interconnections.
A multiplicity of input and output terminals for signal transmission wiring, power supply wiring and clock distribution wiring are indispensable for the semiconductor chip. The optical interconnections, in spite of its advantage of a high speed and a broad band as compared with electric interconnections, cannot reduce the size thereof to the order to wavelength. Considering the delay due to the opto-electric or electro-optic conversion time, on the other hand, the optical interconnections are advantageous over the electric connections only beyond a certain wiring length. It is therefore not advantageous to replace all the electric interconnections with optical ones on a wiring substrate, and it is necessary to secure a certain number of input-output terminals for electric interconnections beforehand. For making electrical and optical interconnections compatible with each other, applying the optical interconnection technique to the flip-chip connection system permitting multi-channel electrical connections is promising.
Two methods are available for performing optical interconnections in a flip-chip connection system: One by interconnecting on the front side and the other on the back side of the semiconductor chip. In a highly-integrated semiconductor chip, however, heat generation is so large that a fin radiator or a cooling channel is formed on the back of the chip. In the flip-chip connection system, therefore, optical interconnections are required on the front, i.e., on the wiring substrate side of the semiconductor chip.
In the aforementioned optical interconnection techniques, the method for forming electrical and optical interconnections on the wiring substrate is not specifically determined. In the case where electrical and optical interconnections are mixed in the same plane of the wiring substrate, for example, the metal forming the electrical wirings does not transmit light, and the dielectric material forming the optical waveguides does not pass electric current. In addition, if electrical wirings are formed on optical waveguides, an optical loss or a change in optical power is a probable result. This has posed the problem of limiting the mutual arrangement of the electrical and optical interconnections.
A clock signal supply system is disclosed in U.S. Pat. No. 5,184,027 and U.S. Pat. No. 5,043,596. In conventional clock signal supply systems, each destination of a clock signal has a phase adjustor in order to reduce the time skew of the clock signal and to automate the phase adjusting process. Such a phase adjuster is supplied with a clock signal and a phase reference signal having a longer period than the clock signal through electric interconnections such as cables or wiring substrate.
Generally, a shorter machine-cycle time, i.e., an improved speed of clock signal is essential for a high-performance operation of the processor.
At the present rate of increase in machine speed, the machine-cycle time, which stands at 7 to 9 nsec in the first half of the 1990s, is expected to decrease to less than 1 nsec in the 2000s, which in turn will require a clock signal of at least 1 GHz in frequency.
Such a ultra-high speed clock signal has not been taken into consideration, however, in designing conventional clock signal supply systems.
Electrical interconnections such as cable and wiring substrate are limited in frequency band by the effect of signal amplitude attenuation due to reactances, reflection caused by impedance mismatch or crosstalks.
In conventional systems, considering the electrical wiring length of several meters and the wiring diameter of less than several millimeters in the processor, it has been very difficult to distribute the clock signal of 1 GHz or more.
Conventional systems for distributing the clock signal by optical interconnections include a configuration comprising a photodetector arranged at each destination of clock signal for distributing the optical clock signal emitted from a light source through such optical paths as optical fiber, optical waveguide, lens and hologram.
The frequency band of optical interconnections is far wider than that of electrical interconnections. It is therefore possible to distribute the optical clock signal of 1 GHz or more in frequency to destinations. The optical clock distribution systems that have been suggested in the prior art, however, have failed to take into consideration the skew due to the difference in optical path length caused by the refractive index distribution, optical aberration, or optical misalignment, or due to variations in the sensitivity or response characteristics of optical detectors.
In a word, according to the prior art systems, the clock signal frequency is undesirably limited by the skew.
Of all the skews, the one due to the difference in optical path length can be reduced by using a programmable optical delay line described in the U.S. Pat. No. 3,516,86 dated May 15, 1989.
The problem of this system, however, is that the operation is very complicated as the distance between two lenses is mechanically changed by manual operation.
When this system is applied to a computer packaged with high density described in F. Kobayashi et al., "Hardware Technology for HITACHI M-880 Processor Group", Proceeding of the 41st Electronic Components and Technology Conference, pp. 693-703, for example, it is extremely difficult to adjust individual optical path lengths manually within a limited package space.
Also, this system still cannot reduce the skew caused by optical detectors.